FIGS. 1 and 2 show steps of manufacturing an NPN bipolar transistor, and more specifically of its emitter contact.
Given an upper region of an epitaxial layer 1 delimited by a thick oxide area 2, a P-type base region 3 has been formed in the surface of the N-type epitaxial layer 1. It will be understood that the epitaxial layer 1 under the base region 3 is a collector region. The structure is coated with an insulating or isolating layer 5 in which an opening 6 is formed, and the whole is coated with a heavily-doped polysilicon layer 8 of type N.sup.+. This is shown in FIG. 1.
In a subsequent step, illustrated in FIG. 2, the polysilicon layer 8 is etched to leave in place a polysilicon pad 10. This pad 10 must be wide enough to be sure that it is not narrower than the opening 6 and to enable to subsequently take a contact on its upper surface by means of a via etched in an insulating layer. After this, lateral spacers 12 are formed at the periphery of the polysilicon pad 10. An emitter diffusion or layer 13 is then formed by fast thermal anneal in the base region 3 from the polysilicon pad 10. The emitter layer 13 forms an NPN bipolar transistor with the base region 3 and the collector region or epitaxial layer 1.
FIG. 3 shows a structure having the same functional characteristics as those of FIG. 2, except that the emitter area has been shown substantially at the center of the base area 3 and thus has a substantially symmetrical outlook. In FIG. 3, the same elements are referred to by same references as in FIG. 2.
In a practical implementation, the opening 6 in the insulating layer 5 has for example a width on the order of 0.5 .mu.m and the insulating layer 5 has for example a width on the order of 80 nm to 120 nm.
To be sure that the polysilicon pad 10 extends beyond the opening 6, it is normally etched from a mask, the lateral dimensions of which are 0.3 .mu.m larger on each side than the dimensions of the opening 6. Thus, this pad 10 has a width of substantially 1.1 .mu.m. It can have the same length or be of triangular shape.
At a further step of the method, it is desired to form a region of higher level of doping 14 for the base contact recovery. This is performed with an implantation 16, for example, a boron implantation. A resist layer 18 has been shown outside the emitter-base area. This resist layer is meant to mask other areas of the integrated circuit formed in the same silicon wafer.
In the manufacturing steps previously described, it has been assumed that, since the polysilicon pad 10 is very heavily N-type doped by an arsenic implantation, the boron implantation 16 is not likely to reverse its type of polarity and disturb the implementation of the N.sup.+ -type heavily-doped emitter diffusion.
However, the applicant has observed defects on this type of component which did not meet the expected specifications, especially as concerns their gain.